FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories
نویسندگان
چکیده
Error correction in high density multilevel cell NAND flash memories is of great concern and Low-DensityParity-Check (LDPC) codes are attracting much interest due to their Shannon-capacity-approaching behavior. In this work, the error performance of very large block length quasi-cyclic (QC) LDPC codes is evaluated through a high speed FPGA based emulator. A novel algebraic QC-LDPC code of rate 0.96 is also proposed for the 8 KB page size of NAND flash memory and its performance is shown. At a frame error rate (FER) of 10−9, the constructed code achieves a coding gain of 0.15 dB with respect to the previously proposed Euclidean geometry QC-LDPC code and does not suffer from any error floor.
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عنوان ژورنال:
- IEEE Design & Test
دوره 33 شماره
صفحات -
تاریخ انتشار 2016